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| NUS3055MUTAG Low Profile Overvoltage Protection IC with Integrated MOSFET This device represents a new level of safety and integration by combining the NCP345 overvoltage protection circuit (OVP) with a 30 V P-channel power MOSFET. It is specifically designed to protect sensitive electronic circuitry from overvoltage transients and power supply faults. During such hazardous events, the IC quickly disconnects the input supply from the load, thus protecting the load before any damage can occur. The OVP IC is optimized for applications that use an external AC-DC adapter or a car accessory charger to power a portable product or recharge its internal batteries. It has a nominal overvoltage threshold of 6.85 V which makes them ideal for single cell Li-Ion as well as 3/4 cell NiCD/NiMH applications. Features http://onsemi.com MARKING DIAGRAM 8 TLLGA8 CASE 517AH XXXX A Y WW G 1 XXXX AYWW G 1 = Specific Device Code = Assembly Location = Year = Work Week = Pb-Free Package * * * * * * * * * OvervoltageTurn-Off Time of Less Than 1.0 ms Accurate Voltage Threshold of 6.85 V, Nominal Undervoltage Lockout Protection; 2.8 V, Nominal High Accuracy Undervoltage Threshold of 2.0% -30 V Integrated P-Channel Power MOSFET Low RDS(on) = 75 mW @ -4.5 V Low Profile 0.55 mm height, 2.5 X 3.0 mm LLGA Package Suitable for Portable Applications Maximum Solder Reflow Temperature @ 260C This device is manufactured with a Pb-Free external lead finish only. PIN CONNECTIONS VCC 8 OUT GATE SRC 7 6 5 DRAIN 4 (Bottom View) 1 IN 2 GND 3 CNTRL 4 DRAIN Benefits * Provide Battery Protection * Integrated Solution Offers Cost and Space Savings * Integrated Solution Improves System Reliability Applications ORDERING INFORMATION Device NUS3055MUTAG Package TLLGA8 (Pb-Free) Shipping 3000 Tape & Reel * Portable Computers and PDAs * Cell Phones and Handheld Products * Digital Cameras For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. (c) Semiconductor Components Industries, LLC, 2006 December, 2006 - Rev. 0 Publication Order Number: NUS3055/D NUS3055MUTAG Schottky Diode VCC SRC P-CH IN Undervoltage Lock Out + - Vref NUS3055 GND CNTRL Microprocessor Port Logic FET Driver GATE + C1 OUT LOAD DRAIN AC/DC Adapter of Accessory Charger Figure 1. Simplified Schematic PIN FUNCTION DESCRIPTIONS Pin # 1 Symbol IN Pin Description This pin senses an external voltage point. If the voltage on this input rises above the overvoltage threshold (VTH), the OUT pin will be driven to within 1.0 V of VCC, thus disconnecting the P-Channel Power MOSFET. The nominal threshold level is 6.85 V and this threshold level can be increased with the addition of an external resistor between IN and VCC. Circuit Ground This logic signal is used to control the state of OUT and turn-on/off the P-Channel Power MOSFET. A logic High results in the OUT signal being driven to within 1.0 V of VCC which disconnects the FET. If this pin is not used, the input should be connected to ground. Drain pin of the P-Channel Power MOSFET Source pin of the P-Channel Power MOSFET Gate pin of the P-Channel Power MOSFET This signal drives the gate of a P-Channel Power MOSFET. It is controlled by the voltage level on IN or the logic state of the CNTRL input. When an overvoltage event is detected, the OUT pin is driven to within 1.0 V of VCC in less than 1.0 _sec provided that gate and stray capacitance is less than 12 nF. Positive Voltage supply. If VCC falls below 2.8 V (nom), the OUT pin will be driven to within 1.0 V of VCC, thus disconnecting the P-channel FET. 2 3 GND CNTRL 4 5 6 7 DRAIN SRC GATE OUT 8 VCC OVERVOLTAGE PROTECTION CIRCUIT TRUTH TABLE IN http://onsemi.com 2 NUS3055MUTAG MAXIMUM RATINGS (TA = 25C unless otherwise stated) Rating OUT Voltage to GND Input and CNTRL Pin Voltage to GND VCC Maximum Range Maximum Power Dissipation (Note 1) Thermal Resistance Junction-to-Air (Note 1) Junction Temperature Operating Ambient Temperature VCNTRL Operating Voltage Storage Temperature Range ESD Performance (HBM) (Note 2) Drain-to-Source Voltage Gate-to-Source Voltage Continuous Drain Current, Steady State, TA = 25C (Note 1) OVP IC P-Channel FET Pin 7 1 3 8 - - - - 3 - 1, 2, 3, 7, 8 Symbol VO Vinput VCNTRL VCC(max) PD RJA TJ TA - Tstg - VDSS VGS ID -20 Min -0.3 -0.3 -0.3 -0.3 - - - -40 0 -65 2.5 Max 30 30 13 30 1.0 342 124 150 85 5.0 150 - -30 20 -1.0 Unit V V V W C/W C C V C kV V V A Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Surface-mounted on FR4 board using 1 inch sq pad size (Cu area = 1.127 in sq [1 oz] including traces). 2. Human body model (HBM): MIL STD 883C Method 3015-7, (R = 1500 W, C = 100 pF, F = 3 pulses delay 1 s). http://onsemi.com 3 NUS3055MUTAG ELECTRICAL CHARACTERISTICS (TA= 25C, Vcc = 6.0 V, unless otherwise specified) Characteristic VCC Operating Voltage Range Supply Current (ICC + IInput; VCC = 6.0 V Steady State) Input Threshold (VInput connected to VCC; VInput increasing) Input Hysteresis (VInput connected to VCC; VInput decreasing) Input Impedance (Input = VTh) CNTRL Voltage High CNTRL Voltage Low CNTRL Current High (Vih = 5.0 V) CNTRL Current Low (Vil = 0.5 V) Undervoltage Lockout (VCC decreasing) Output Sink Current (VCC < VTh, VOUT = 1.0 V) Output Voltage High (VCC = Vin = 8.0 V; ISource = 10 mA) Output Voltage High (VCC = Vin = 8.0 V; ISource = 0.25 mA) Output Voltage High (VCC = Vin = 8.0 V; ISource = 0 mA) Output Voltage Low (Input < 6.5 V; ISink = 0 mA; VCC = 6.0 V, CNTRL = 0 V) Turn ON Delay - Input (Note 3) (VInput connected to VCC; VInput step down signal from 8.0 to 6.0 V; measured to 50% point of OUT)* Turn OFF Delay - Input (VInput connected to VCC; VInput step up signal from 6.0 to 8.0 V; CL = 12 nF Output > VCC - 1.0 V) Turn ON Delay - CNTRL (CNTRL step down signal from 2.0 to 0.5 V; measured to 50% point of OUT) (Note 3) Turn OFF Delay - CNTRL (CNTRL step up signal from 0.5 to 2.0 V; CL = 12 nF Output > VCC -1.0 V) 3. Guaranteed by design. Symbol VCC(opt) - VTh VHyst Rin Vih Vil Iih Iil VLock ISink Voh Pin 8 1, 8 1 1 1 3 3 3 3 3 7 7 Min 3.0 - 6.65 50 70 1.5 - - - 2.5 10 VCC-1.0 VCC-0.25 VCC-0.1 - - Typ 4.8 0.75 6.85 100 150 - - 95 10 2.8 33 - Max 25 1.0 7.08 200 - - 0.5 200 20 3.0 50 - Unit V mA V mV kW V V mA mA V mA V Vol TON IN 7 7 - - 0.1 10 V ms TOFF IN TON CT TOFF CT 7 7 7 - - - 0.5 - 1.0 1.0 10 2.0 ms ms ms P-CHANNEL MOSFET (TA= 25C unless otherwise specified) Parameter Drain to Source On Resistance (VGS = -4.5 V, ID = 600 mA) (VGS = -4.5 V, ID = 1.0 A) Zero Gate Voltage Drain Current (VGS = 0 V, VDS = -24 V) Turn On Delay (Note 4) (VGS = -4.5 V, ID = -1.0 A, RG = 6.0 W, VDS = 15 V) Turn Off Delay (Note 4) (VGS = -4.5 V, ID = -1.0 A, RG = 6.0 W, VDS = 15 V) Input Capacitance (Note 3) (VGS = 0 V, f = 1.0 MHz, VDS = -15 V) Gate to Source Leakage Current (VGS = 20 V, VDS = 0 V) Drain to Source Breakdown Voltage (VGS = 0 V, ID = -250 mA) Gate Threshold Voltage (VGS = VDS, ID = -250 mA) Symbol RDS(on) 66 66 IDSS -1.0 ton 11 toff 28 Cin 750 IGSS 10 V(BR)DSS 30 V(GS)th -3.0 -1.0 V V nA pF ns ns 110 110 mA Min Typ Max Units mW 4. Switching characteristics are independent of operating junction temperature. http://onsemi.com 4 NUS3055MUTAG TYPICAL PERFORMANCE CURVES (TA= 25C, unless otherwise specified) OVERVOLTAGE PROTECTION IC 7.05 7.00 0.9 I supply (mA) 6.95 Voltage (V) 6.90 6.85 6.80 0.6 6.75 6.70 -40 0.5 -40 1.0 0.8 0.7 -25 -10 5 20 35 50 65 80 95 -25 -10 5 20 35 50 65 80 95 Ambient Temperature (C) Temperature (C) Figure 2. Typical Vth Threshold Variation vs. Temperature Figure 3. Typical Supply Current vs. Temperature Icc ) Iin, VCC + 6 V http://onsemi.com 5 NUS3055MUTAG TYPICAL PERFORMANCE CURVES (TA= 25C, unless otherwise specified) 30 V, P-CHANNEL MOSFET RDS(on), DRAIN-TO-SOURCE RESISTANCE (W) 12 -ID, DRAIN CURRENT (AMPS) 11 10 9 8 7 6 5 4 3 2 1 0 -10V -4.5 V -4.2 V -8 V -6 V -5.5 V -5 V -4 V 0.2 TJ = 25C ID = -3.7 A -3.8 V -3.6 V -3.4 V -3.2 V -3 V TJ = 25C 0.1 0 2 3 4 5 6 7 8 9 10 -VGS, GATE VOLTAGE (VOLTS) 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) Figure 4. On-Region Characteristics 100000 -IDSS, LEAKAGE CURRENT (nA) -IS, SOURCE CURRENT (AMPS) VGS = 0 V TJ = 150C 10 Figure 5. On-Resistance vs. Gate-to-Source Voltage VGS = 0 V TJ = 150C 10000 1 TJ = 100C TJ = 25C 1000 TJ = 100C 100 5 10 15 20 25 -VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 30 0.1 0.3 TJ = -55C 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 -VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS) Figure 6. Drain-to-Source Leakage Current vs. Voltage Figure 7. Diode Forward Voltage vs. Current http://onsemi.com 6 NUS3055MUTAG TYPICAL APPLICATION CIRCUITS & OPERATION WAVEFORMS (TA= 25C, unless otherwise specified) VCC P-CH IN Undervoltage Lock Out + - Vref 6 Vdc 8 Vdc NUS3055 GND CNTRL Logic FET Driver GATE 12 W OUT Figure 8. Test Circuit for TON IN and TOFF IN Input Voltage TON IN Output Voltage TON IN Test TA=25C Figure 9. TON IN Waveforms http://onsemi.com 7 NUS3055MUTAG TOFF IN Input Voltage TOFF IN Test TA=25C Output Voltage Figure 10. TOFF IN Waveforms VCC P-CH IN Undervoltage Lock Out + - Vref 6 Vdc 8 Vdc NUS3055 GND CNTRL Logic FET Driver GATE 12 W OUT Figure 11. Test Circuit for TON CT and TOFF CT http://onsemi.com 8 NUS3055MUTAG TON CT CNTR signal Input Voltage Output Voltage TON CT Test TA=25C Figure 12. TON CT Waveforms TOFF CT CNTR signal Input Voltage TOFF CT Test TA=25C Output Voltage Figure 13. TOFF CT Waveforms http://onsemi.com 9 NUS3055MUTAG PACKAGE DIMENSIONS LLGA8 3x2.5, 0.65P CASE 517AH ISSUE A D AB NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20mm FROM TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 b b2 D D2 E E2 e G K L SEATING PLANE MILLIMETERS MIN MAX 0.50 0.60 0.00 0.05 0.35 0.45 0.45 0.55 3.00 BSC 1.25 1.35 2.50 BSC 1.55 1.65 0.65 BSC 0.05 REF 0.15 REF 0.35 0.45 PIN ONE REFERENCE 2X 0.10 C 2X 0.10 C 0.10 C 6X 0.08 C b2 4X K 0.55 E2 8 8X 5 L BOTTOM VIEW 8X b 0.10 C A B 0.05 C NOTE 3 1.35 1.50 *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 10 CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC CC EEE EEE EEE G 1 E TOP VIEW A SIDE VIEW A1 D2 4 C SOLDERING FOOTPRINT* 2.80 1 8X e 0.45 0.45 7X 0.03 0.65 PITCH DIMENSIONS: MILLIMETERS NUS3055/D |
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